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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
EXTERNAL PIN STATUS
The 10XS3535 provides the status of the FLASHER, FOG,
and IGN pins via the SPI in real time and in Normal mode.
FAILURE HANDLING STRATEGY
A highly sophisticated failure handling strategy enables
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
? Reverse Polarity
? Loss of Supply Lines
? Fatal Mistreatment of Logic I/O Pins
REVERSE POLARITY PROTECTION ON VBAT
In case of a permanently reverse polarity operation, the
output transistors are turned ON (Rsd) to prevent thermal
overloads and no protections are available.
An external diode on VCC is necessary in order to not to
destroy the 10XS3535 in cases of reverse polarity.
In case of negative transients on the V BAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Without loads on OUT1:5 terminal, an external
clamp between V BAT and GND is mandatory to avoid
exceeding maximum rating. The maximum external clamp
voltage shall be between the reverse battery condition and ?
-20 V.
Therefore, the device is protected against latch-up with or
without load on OUT outputs.
LOSS OF SUPPLY LINES
The 10XS3535 is protected against the loss of any supply
line. The detection of the supply line failure is provided inside
the device itself.
LOSS OF VBAT
During an under-voltage of V BAT (V BATPOR1 <
V BAT < V BATUV ), the outputs [1-5] are switched off
immediately. No current path from VBAT to VCC. The
external MOSFET (OUT6) can be controlled in Normal Mode
? all latched faults are maintained under V CC in nominal
conditions. In case V BAT is disconnected, OUT[1:5]
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting (if V BAT was previously in the nominal voltage
range for at least 35 ? sec), and daisy-chain features are
provided for RST is set to logic [1]. The SPI pull-up and
pull-down current resistors are available. This fault
condition can be diagnosed with UVF fault in OD13
reporting bit. The previous device configuration is
maintained. No current is conducted from V CC to V BAT .
LOSS OF V CC (DIGITAL LOGIC SUPPLY LINE)
During loss of V CC (V CC < V CCUV ) and with wake=1, the
10XS3535 is switched automatically into Fail mode (no
deglich time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when V CC
goes above V CCUV . The device will transit in OFF mode if
VBAT < V BATPOR2 .
LOSS OF V CC AND VBAT
If the external V BAT and V CC supplies are disconnected (or
not within specification: (V CC and V BAT ) < V BATPOR1 ), all SPI
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
LOSS OF GROUND (GND)
During loss of ground, the 10XS3535 cannot operate the
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1kohm typical). The state of the external
smart power switch controlled by FETOUT is not guaranteed,
and the state of external smart MOS is defined with an
external termination resistor.
FATAL MISTREATMENT OF LOGIC I / O PINS
The digital I / Os are protected against fatal mistreatment
Table 16. Logic I / O Plausibility Check
by the SPI if VCC remains and is above V CCUV . The fault is
reported to the UVF bit (OD13). To delatch the fault, the
under-voltage condition should be removed and:
? To turn-on the output, the corresponding D7 bit must be
rewritten to logic [1] in Normal mode. Application of the
OCHI window depends on toggling or not toggling the
D7 bit.
Input / Output
LIMP
(PWM) CLOCK
SPI (MOSI, SCLK, CS )
Signal Check Strategy
Debounce for 10ms
Frequency range
(bandpass filter)
WD, D10 bit internal toggle
? If the device was in Fail mode, the fault will be delatched
by the Autorestart feature periodically.
In case of V BAT < V BATPOR1 (Power OFF mode), the
behavior depends on V CC :
? all latched faults are reset if VCC < V CCUV ,
In case the LIMP input is set to logic [1] for a delay longer
than 10ms typical, the 10XS3535 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is provided
and the bit D7 defines the outputs state. In case of SPI failure,
MC10XS3535
Analog Integrated Circuit Device Data ?
38
Freescale Semiconductor
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